Integrated circuit die may be designed such that they may be stacked on top of one another to form a stacked die arrangement. The stacked die arrangement may be further mounted upon a silicon interposer layer/die. The silicon interposer serves as a signal redistribution layer for connecting the fine pitch contact points of the stacked die to wider pitch contact points of a substrate, such as, but not limited too, a board. Prior to mounting onto a substrate the stacked die and interposer ensemble must be tested to assure goodness. Testing is done by connecting a tester to the interposer and applying test patterns to the stacked die via the interposer.
FIG. 1 illustrates a device 100 including a stack of die 102-104 mounted upon a conventional silicon interposer 106. The interposer 106 is further mounted to a substrate 108, such as, but not limited too, a smart phone printed circuit board (PCB), a desk top computer PCB, a lap top computer PCB, a tablet PCB or another die. The die 102-104 in this example are designed using Through Silicon Vias (TSV) 110. TSVs are connectivity paths formed between the top and bottom surfaces of the die. TSVs allow substrate input 118 and output 120 signals to flow vertically up and down the die stack via the interposer to provide input to and output from the die circuitry 112 of each die. The die 102-104 are locally connected together via connections 114. The signal connections between die 102 and 104, between die 104 and interposer 106 and between interposer 106 and substrate 108 are indicated by contact points 116.
FIG. 2 is provided to illustrate the redistribution layer function of the interposer 106 to spread connections from fine pitch contact points 116 of die 104 to wider pitch contact points 116 of the substrate 108.
FIG. 3 is a schematic representation of the die stack and interposer of FIG. 1 that will be used to facilitate the description of the disclosure. For simplicity, the local die connections 114 are not shown in FIG. 3.
FIG. 4 illustrates die circuitry 112 which includes functional circuitry 402 for performing the functional operation of the die and embedded test circuitry 404 for testing the functional circuitry. The inputs 118 and outputs 120 of the die circuitry 112 are coupled to the functional 402 and test circuitry 404. During functional operations the functional circuitry operates by inputting functional signals from inputs 118 and outputting functional signals to outputs 120. During test operations the test circuitry operates by inputting test stimulus and test control signals from some or all of the inputs 118 and outputting test response signals to some or all of the outputs 120.
FIG. 5 illustrates a tester 502 connected to the interposer 106 to input stimulus (S) and control (C) signals to the test circuitry 404 of die 102 and 104 and to receive response (R) signals from the test circuitry 404 of die 102 and 104. The stimulus and control signals are input from the tester using some or all of the inputs 118 and the response signals are output to the tester using some or all of the outputs 120.
The following disclosure describes a new method of controlling the test circuitry 404 of die 102 and 104. The new method is achieved by embedding die test and access circuitry within the interposer 106.